Default Enviroment settings in DFTAdvisor

Gate Level = design
Gate Report = normal
Net Resolution = wire
System Mode = setup
Tied Signal = x
Dofile Abort = on
Trace Report = off
Scan Type = mux_scan
Identification Model = clock:original disturb:on
Scan Identification = full_scan
Test_point Identification = control:0 observe:0 (scoap)
Transient Detection = on -verbose
Fault Sampling = 100.000000%
Scan-in Naming = prefix:scan_in initial:1 modifier:1 suffix:
Scan-out Naming = prefix:scan_out initial:1 modifier:1 suffix:
Test Enable Name = test_en active = high
Test Clock Name = test_clk
Scan Enable Name (Core)= scan_en active = high
Scan Enable Name (Input Partition)= scan_en_in active = high
Scan Enable Name (Output Partition)= scan_en_out active = high
Scan Clock Name = scan_clk
Scan Master Clock Name = scan_mclk
Scan Slave Clock Name = scan_sclk
Set Name = scan_set active = high muxed
Reset Name = scan_reset active = high muxed
Write Clock Name = write_clk muxed
Read Clock Name = read_clk muxed
Hold Enable Name = hold_en
Control Input Name = test_cntl
Observe Output Name = test_obs
Net Naming = net Instance Naming = uu
Test Logic = set:off reset:off clock:off tristate:off bidi:off ram:off
Logfile = dfta.log
Screen Display = off
Lockup Latch = off nolast first_clock
Latch Handling = none

Writing a Test Procedure file

Test procedure files describe the scan circuitry’s operation for the ATPG tool. They contain cycle based procedures and timing definitions that tell the DFT tools how to operate the scan structures in the design.

Before running ATPG you must be ready with a test procedure file to proceed further.

To specify a test procedure file in setup mode, use the Add Scan Groups command. The tools can also read in procedure files by using the Read Procfile command or the Save Patterns command when not in Setup mode. When you load more than one test procedure file, the tool merges the timing and procedure data.

Following are the standard test procedures: – test_setup, load_unload, shift Continue reading

Troubleshooting DRC Violations

Some rules permit user-defined handling, allowing you to specify either error, warning, note, or ignore as the handling for certain rules. (use set drc handling command)

Setting the level of Gate Data using set gate level command. The gate level can be set to design level or primitive level. When the gate level is set to design level only you will be able to correlate the reported gate to the library model available in your netlist. When the design level is set to primitive level such correlation is possible to a limited extent and the reported gate can sometimes be nowhere found in the netlist.

The set gate report command sets the type of information you want to be displayed when you report a gate. You can set that to Normal or Trace or Error_pattern or tie_value

You can use the Report Gates command to display information for selected gates, which you identify by either a gate index number or a pin pathname of a pin connected to the gate. Report Gate is a very useful command. You can list all gates of a specific type using the -type switch and a histogram of all gates by setting the type to histogram. You can report on a path between two gates. you can browse back and forth using the f and b commands respectively.

Fastscan DRC

RAM Rules: A1 to A7, A9 to A13

Clock Rules: C1 to C10 and C16

Data Rules : D1 to D11

Extra Rules: E1 to E13

General Rules: G1 to G12

Procedure Rules: P1 to P70

Trace Rules: T1 to T24

Timing Rules: W1 to W15, W17 to W18, W20 to W31

ATPG Design Rules Checking

Design rules checking generally consists of the following processes, done in the order shown:
1. General Rules Checking
2. Procedure Rules Checking
3. Bus Mutual Exclusivity Analysis
4. Scan Chain Tracing
5. Shadow Latch Identification
6. Data Rules Checking
7. Transparent Latch Identification
8. Clock Rules Checking
9. RAM Rules Checking
10. Bus Keeper Analysis
11. Extra Rules Checking
12. Scannability Rules Checking
13. Constrained/Forbidden/Block Value Calculations

Mentor Tool Concepts

A scan cell contains atleast one memory element (flip-flop or latch) that lies in the scan chain path.

Master Memory Element

The scan cell contains one and only one master memory element and one or more optional salve memory elements. The Shift Procedure in the test procedure file controls the master element.If the scan cell contains no additional independently-clocked memory elements in the scan path, this procedure also observes the master. If the scan cell contains additional memory elements, you may need to define a separate observation procedure (called master_observe) for propagating the master element’s value to the output of the scan cell.

Slave Memory Element

The slave element, an independently-clocked scan cell memory element, resides in the scan chain path. It cannot capture data directly from the previous scan cell. When used, it stores the output of the scan cell. The shift procedure both controls and observes the slave element.

Scan Chain

A scan chain is a set of serially linked scan cells

Scan Group

A scan chain group is a set of scan chains that operate in parallel and share a common test procedure file.

Scan Clocks

Scan clocks are external pins capable of capturing values into scan cell elements. Scan clocks include set and reset lines, as well as traditional clocks.

Test Procedure files

Test procedure files describe, for the ATPG tool, the scan circuitry operation within a design.

  • Define the scan circuitry for the tool.
  • Create a test procedure file to describe the scan circuitry operation. DFTAdvisor can create test procedure files for you.
  • Perform DRC process. This occurs when you exit from Setup mode.

If your design contains scan circuitry, FastScan and FlexTest require a test procedure file. You must create one before running ATPG with FastScan or FlexTest.

Model Flattening

The tools flatten the model when you initially attempt to exit the Setup mode, just prior to design rules checking. FastScan and FlexTest also provide the Flatten Model command, which allows flattening of the design model while still in Setup mode.

If a flattened model already exists when you exit the Setup mode, the tools will only reflatten the model if you have since issued commands that would affect the internal representation of the design. For example, adding or deleting primary inputs, tying signals, and changing the internal faulting strategy are changes that affect the design model. With these types of changes, the tool must re-create or re-flatten the design model. If the model is undisturbed, the tool keeps the original flattened model and does not attempt to reflatten.

By default, pins introduced by the flattening process remain unnamed and are not valid fault sites.

You should be aware that in some cases, the design flattening process can appear to introduce new gates into the design.

Learning Analysis

There are two types of learning analysis:-

Static Learning

Dynamic Learning

The ATPG tools perform static learning only once-after flattening. Because pin and ATPG constraints can change the behavior of the design, static learning does not consider these constraints. Static learning involves gate-by-gate local simulation to determine information about the design. The following subsections lists the types of analysis performed during static learning.

  • Equivalence Relationships
  • Logic Behavior
  • Implied Relationships
  • Forbidden Relationships
  • Dominance Relationships

Fault Classes – Mentor Terminology

  • Untestable Faults – UT
    • Unused – UU
    • Tied – TI
    • Blocked – BL
    • Redundant – RE
  • Testable Faults
    • Detected – DT
      • det_simulation – DS (faults detected when the tool performs fault simulation)
      • det_implication – DI (faults detected when the tool performs learning analysis)
      • det_robust
      • det_functional
    • Posdet – PD
      • posdet-testable – PT (Can be detected by increasing the test generator abort limit)
      • posdet-untestable – PU
    • ATPG Untestable – AU (Cannot be detected by increasing the test generator abort limit)
    • Undetected – UD
      • Uncontrolled – UC
      • Unobserved – UO