What is the difference between Serail and Parallel Patterns

Parallel patterns are forced parallely (at the same instance of time) @ SI of each flop and measured @ SO. Basically these patterns are used for simulating the patterns faster. Here only two cycles are required to simulate a pattern : one to force all the flops and one for capture.
Serial patterns are the ones which are used @the tester. They are serially shifted and captured and shifted out.

Fastscan DRC

RAM Rules: A1 to A7, A9 to A13

Clock Rules: C1 to C10 and C16

Data Rules : D1 to D11

Extra Rules: E1 to E13

General Rules: G1 to G12

Procedure Rules: P1 to P70

Trace Rules: T1 to T24

Timing Rules: W1 to W15, W17 to W18, W20 to W31

ATPG Design Rules Checking

Design rules checking generally consists of the following processes, done in the order shown:
1. General Rules Checking
2. Procedure Rules Checking
3. Bus Mutual Exclusivity Analysis
4. Scan Chain Tracing
5. Shadow Latch Identification
6. Data Rules Checking
7. Transparent Latch Identification
8. Clock Rules Checking
9. RAM Rules Checking
10. Bus Keeper Analysis
11. Extra Rules Checking
12. Scannability Rules Checking
13. Constrained/Forbidden/Block Value Calculations

Fault Classes – Mentor Terminology

  • Untestable Faults – UT
    • Unused – UU
    • Tied – TI
    • Blocked – BL
    • Redundant – RE
  • Testable Faults
    • Detected – DT
      • det_simulation – DS (faults detected when the tool performs fault simulation)
      • det_implication – DI (faults detected when the tool performs learning analysis)
      • det_robust
      • det_functional
    • Posdet – PD
      • posdet-testable – PT (Can be detected by increasing the test generator abort limit)
      • posdet-untestable – PU
    • ATPG Untestable – AU (Cannot be detected by increasing the test generator abort limit)
    • Undetected – UD
      • Uncontrolled – UC
      • Unobserved – UO

Why At-speed testing?

Why are stuck-at faults more efficient when applied at the circuit’s rated clock?

Timing failures can occur when a circuit operates correctly at a slow clock rate, and then fails when run at the normal system speed. In other words, when stuck-at fault tests are applied at a slower clock rate some faults which are a manifestation of timing failures could not have been detected. Such faults, if present will fail the chip ultimately. Hence At-Speed testing which is nothing but applying tests at the rated clock speed could detect such chips which are bound to fail due to timing failures.

Random Vs Deterministic Test Pattern Generation

Random Test Pattern Generation – RTPG

Deterministic Test Pattern Generation – DTPG

RTPG can never identify redundant faults while DTPG does. However, it can be useful on testable faults terminated by DTPG. Hence, as an initial step using a small number of random patterns can improve ATPG performance.

The very definition of RTPG and DTPG can prove the above statement. In DTPG, also called ATPG, there are some algorithms used to find a pattern that detects a particular fault. These ATPG algorithms have the ability to find if a fault is redundant or not. There are algorithms(called Redundancy Identification RID algorithms) which analyze the circuit without targeting any specific faults and can find many, but not all, redundant faults.

Whereas RTPG, like in Logic BIST, applies random vectors and tries to choose the best minimum possible patterns targeting a particular fault coverage. (The coverage of random patterns is observed to saturate between 60-80% of coverage)