A scan cell contains atleast one memory element (flip-flop or latch) that lies in the scan chain path.
Master Memory Element
The scan cell contains one and only one master memory element and one or more optional salve memory elements. The Shift Procedure in the test procedure file controls the master element.If the scan cell contains no additional independently-clocked memory elements in the scan path, this procedure also observes the master. If the scan cell contains additional memory elements, you may need to define a separate observation procedure (called master_observe) for propagating the master element’s value to the output of the scan cell.
Slave Memory Element
The slave element, an independently-clocked scan cell memory element, resides in the scan chain path. It cannot capture data directly from the previous scan cell. When used, it stores the output of the scan cell. The shift procedure both controls and observes the slave element.
A scan chain is a set of serially linked scan cells
A scan chain group is a set of scan chains that operate in parallel and share a common test procedure file.
Scan clocks are external pins capable of capturing values into scan cell elements. Scan clocks include set and reset lines, as well as traditional clocks.
Test Procedure files
Test procedure files describe, for the ATPG tool, the scan circuitry operation within a design.
- Define the scan circuitry for the tool.
- Create a test procedure file to describe the scan circuitry operation. DFTAdvisor can create test procedure files for you.
- Perform DRC process. This occurs when you exit from Setup mode.
If your design contains scan circuitry, FastScan and FlexTest require a test procedure file. You must create one before running ATPG with FastScan or FlexTest.
The tools flatten the model when you initially attempt to exit the Setup mode, just prior to design rules checking. FastScan and FlexTest also provide the Flatten Model command, which allows flattening of the design model while still in Setup mode.
If a flattened model already exists when you exit the Setup mode, the tools will only reflatten the model if you have since issued commands that would affect the internal representation of the design. For example, adding or deleting primary inputs, tying signals, and changing the internal faulting strategy are changes that affect the design model. With these types of changes, the tool must re-create or re-flatten the design model. If the model is undisturbed, the tool keeps the original flattened model and does not attempt to reflatten.
By default, pins introduced by the flattening process remain unnamed and are not valid fault sites.
You should be aware that in some cases, the design flattening process can appear to introduce new gates into the design.
There are two types of learning analysis:-
The ATPG tools perform static learning only once-after flattening. Because pin and ATPG constraints can change the behavior of the design, static learning does not consider these constraints. Static learning involves gate-by-gate local simulation to determine information about the design. The following subsections lists the types of analysis performed during static learning.
- Equivalence Relationships
- Logic Behavior
- Implied Relationships
- Forbidden Relationships
- Dominance Relationships