Parallel patterns are forced parallely (at the same instance of time) @ SI of each flop and measured @ SO. Basically these patterns are used for simulating the patterns faster. Here only two cycles are required to simulate a pattern : one to force all the flops and one for capture.
Serial patterns are the ones which are used @the tester. They are serially shifted and captured and shifted out.
DFT
The DFTAdvisor commands that support instance-expressions are:
Add Nonscan Instances
Add Notest Points
Add Scan Instances
Add Nofaults
Delete Nofaults
Delete Notest Points
Delete Nonscan Instances
Delete Scan Instances
Default Enviroment settings in DFTAdvisor
Gate Level = design
Gate Report = normal
Net Resolution = wire
System Mode = setup
Tied Signal = x
Dofile Abort = on
Trace Report = off
Scan Type = mux_scan
Identification Model = clock:original disturb:on
Scan Identification = full_scan
Test_point Identification = control:0 observe:0 (scoap)
Transient Detection = on -verbose
Fault Sampling = 100.000000%
Scan-in Naming = prefix:scan_in initial:1 modifier:1 suffix:
Scan-out Naming = prefix:scan_out initial:1 modifier:1 suffix:
Test Enable Name = test_en active = high
Test Clock Name = test_clk
Scan Enable Name (Core)= scan_en active = high
Scan Enable Name (Input Partition)= scan_en_in active = high
Scan Enable Name (Output Partition)= scan_en_out active = high
Scan Clock Name = scan_clk
Scan Master Clock Name = scan_mclk
Scan Slave Clock Name = scan_sclk
Set Name = scan_set active = high muxed
Reset Name = scan_reset active = high muxed
Write Clock Name = write_clk muxed
Read Clock Name = read_clk muxed
Hold Enable Name = hold_en
Control Input Name = test_cntl
Observe Output Name = test_obs
Net Naming = net Instance Naming = uu
Test Logic = set:off reset:off clock:off tristate:off bidi:off ram:off
Logfile = dfta.log
Screen Display = off
Lockup Latch = off nolast first_clock
Latch Handling = none
Mentor Tool Concepts
A scan cell contains atleast one memory element (flip-flop or latch) that lies in the scan chain path.
Master Memory Element
The scan cell contains one and only one master memory element and one or more optional salve memory elements. The Shift Procedure in the test procedure file controls the master element.If the scan cell contains no additional independently-clocked memory elements in the scan path, this procedure also observes the master. If the scan cell contains additional memory elements, you may need to define a separate observation procedure (called master_observe) for propagating the master element’s value to the output of the scan cell.
Slave Memory Element
The slave element, an independently-clocked scan cell memory element, resides in the scan chain path. It cannot capture data directly from the previous scan cell. When used, it stores the output of the scan cell. The shift procedure both controls and observes the slave element.
Scan Chain
A scan chain is a set of serially linked scan cells
Scan Group
A scan chain group is a set of scan chains that operate in parallel and share a common test procedure file.
Scan Clocks
Scan clocks are external pins capable of capturing values into scan cell elements. Scan clocks include set and reset lines, as well as traditional clocks.
Test Procedure files
Test procedure files describe, for the ATPG tool, the scan circuitry operation within a design.
- Define the scan circuitry for the tool.
- Create a test procedure file to describe the scan circuitry operation. DFTAdvisor can create test procedure files for you.
- Perform DRC process. This occurs when you exit from Setup mode.
If your design contains scan circuitry, FastScan and FlexTest require a test procedure file. You must create one before running ATPG with FastScan or FlexTest.
Model Flattening
The tools flatten the model when you initially attempt to exit the Setup mode, just prior to design rules checking. FastScan and FlexTest also provide the Flatten Model command, which allows flattening of the design model while still in Setup mode.
If a flattened model already exists when you exit the Setup mode, the tools will only reflatten the model if you have since issued commands that would affect the internal representation of the design. For example, adding or deleting primary inputs, tying signals, and changing the internal faulting strategy are changes that affect the design model. With these types of changes, the tool must re-create or re-flatten the design model. If the model is undisturbed, the tool keeps the original flattened model and does not attempt to reflatten.
By default, pins introduced by the flattening process remain unnamed and are not valid fault sites.
You should be aware that in some cases, the design flattening process can appear to introduce new gates into the design.
Learning Analysis
There are two types of learning analysis:-
Static Learning
Dynamic Learning
The ATPG tools perform static learning only once-after flattening. Because pin and ATPG constraints can change the behavior of the design, static learning does not consider these constraints. Static learning involves gate-by-gate local simulation to determine information about the design. The following subsections lists the types of analysis performed during static learning.
- Equivalence Relationships
- Logic Behavior
- Implied Relationships
- Forbidden Relationships
- Dominance Relationships
Fault Classes – Mentor Terminology
- Untestable Faults – UT
- Unused – UU
- Tied – TI
- Blocked – BL
- Redundant – RE
- Testable Faults
- Detected – DT
- det_simulation – DS (faults detected when the tool performs fault simulation)
- det_implication – DI (faults detected when the tool performs learning analysis)
- det_robust
- det_functional
- Posdet – PD
- posdet-testable – PT (Can be detected by increasing the test generator abort limit)
- posdet-untestable – PU
- ATPG Untestable – AU (Cannot be detected by increasing the test generator abort limit)
- Undetected – UD
- Uncontrolled – UC
- Unobserved – UO
- Detected – DT
Script for generation of a selective IDDQ test set
After generating patterns for stuck at faults and saving the patterns into a file say pat_file
set pattern source external pat_file
set fault type iddq
add faults -all
set iddq strobe -all
select iddq patterns -max_measure 15 -threshold 10 (to select best 15 patterns that detect a min of 10 IDDQ faults each
save patterns iddq.pats
Points to note
- Fault modeling occurs at various level of detail. e.g. Transistor level, Gate level etc
- FastScan does equivalence fault collapsing before going for pattern generation
- Generally, ASIC vendors have restrictions on the number of IDDQ measurements they allow.
- By combining IDDQ testing with traditional stuck-at fault testing, you can greatly improve the overall test coverage of your design.
- You can turn dynamic pattern compression on with the Set Atpg Compression On command in FastScan
- Each scan pattern is as long as the longest scan chain. So it is desirable to have balanced scan chains to the extent possible.
- The ATE (Automatic Test Equipment) also imposes limitations on the number of allowable scan chains in a design.
- Lock up Latches can be used in a scan chain to avoid race conditions(hold time violatoins) that occur due to clock skew
- Always group the negedge flops and place them in the begining of the scan chain or you will have to insert a lockup latch whenever a negedge flop follows a posedge flop in a scan chain.
- Exclude flip flops that constitute reset and clock generation circuits
Points to Probe
- what is a psuedo stuck at fault model?
- Add Pin Constraint command in FastScan
- Update Implication Detections command in FastScan
Why At-speed testing?
Why are stuck-at faults more efficient when applied at the circuit’s rated clock?
Timing failures can occur when a circuit operates correctly at a slow clock rate, and then fails when run at the normal system speed. In other words, when stuck-at fault tests are applied at a slower clock rate some faults which are a manifestation of timing failures could not have been detected. Such faults, if present will fail the chip ultimately. Hence At-Speed testing which is nothing but applying tests at the rated clock speed could detect such chips which are bound to fail due to timing failures.
Random Vs Deterministic Test Pattern Generation
Random Test Pattern Generation – RTPG
Deterministic Test Pattern Generation – DTPG
RTPG can never identify redundant faults while DTPG does. However, it can be useful on testable faults terminated by DTPG. Hence, as an initial step using a small number of random patterns can improve ATPG performance.
The very definition of RTPG and DTPG can prove the above statement. In DTPG, also called ATPG, there are some algorithms used to find a pattern that detects a particular fault. These ATPG algorithms have the ability to find if a fault is redundant or not. There are algorithms(called Redundancy Identification RID algorithms) which analyze the circuit without targeting any specific faults and can find many, but not all, redundant faults.
Whereas RTPG, like in Logic BIST, applies random vectors and tries to choose the best minimum possible patterns targeting a particular fault coverage. (The coverage of random patterns is observed to saturate between 60-80% of coverage)
Prasad Addagarla 