Fastscan DRC

RAM Rules: A1 to A7, A9 to A13

Clock Rules: C1 to C10 and C16

Data Rules : D1 to D11

Extra Rules: E1 to E13

General Rules: G1 to G12

Procedure Rules: P1 to P70

Trace Rules: T1 to T24

Timing Rules: W1 to W15, W17 to W18, W20 to W31

ATPG Design Rules Checking

Design rules checking generally consists of the following processes, done in the order shown:
1. General Rules Checking
2. Procedure Rules Checking
3. Bus Mutual Exclusivity Analysis
4. Scan Chain Tracing
5. Shadow Latch Identification
6. Data Rules Checking
7. Transparent Latch Identification
8. Clock Rules Checking
9. RAM Rules Checking
10. Bus Keeper Analysis
11. Extra Rules Checking
12. Scannability Rules Checking
13. Constrained/Forbidden/Block Value Calculations