Can all the test signals be shared

In a Scan based design for testability we generally need the following test signals

  • scan_in
  • scan_out
  • scan_en
  • test_mode(optional)
If you are having only the first three test signals then you need to have scan_en dedicated and the rest two can be shared. However, it is recommended to use all the above listed signals wherein only test_mode will be dedicated and the rest can be shared. This dedicated test_mode signal can be used to control other non-scan test logic inserted into the design. 

What is the difference between Serail and Parallel Patterns

Parallel patterns are forced parallely (at the same instance of time) @ SI of each flop and measured @ SO. Basically these patterns are used for simulating the patterns faster. Here only two cycles are required to simulate a pattern : one to force all the flops and one for capture.
Serial patterns are the ones which are used @the tester. They are serially shifted and captured and shifted out.

Default Enviroment settings in DFTAdvisor

Gate Level = design
Gate Report = normal
Net Resolution = wire
System Mode = setup
Tied Signal = x
Dofile Abort = on
Trace Report = off
Scan Type = mux_scan
Identification Model = clock:original disturb:on
Scan Identification = full_scan
Test_point Identification = control:0 observe:0 (scoap)
Transient Detection = on -verbose
Fault Sampling = 100.000000%
Scan-in Naming = prefix:scan_in initial:1 modifier:1 suffix:
Scan-out Naming = prefix:scan_out initial:1 modifier:1 suffix:
Test Enable Name = test_en active = high
Test Clock Name = test_clk
Scan Enable Name (Core)= scan_en active = high
Scan Enable Name (Input Partition)= scan_en_in active = high
Scan Enable Name (Output Partition)= scan_en_out active = high
Scan Clock Name = scan_clk
Scan Master Clock Name = scan_mclk
Scan Slave Clock Name = scan_sclk
Set Name = scan_set active = high muxed
Reset Name = scan_reset active = high muxed
Write Clock Name = write_clk muxed
Read Clock Name = read_clk muxed
Hold Enable Name = hold_en
Control Input Name = test_cntl
Observe Output Name = test_obs
Net Naming = net Instance Naming = uu
Test Logic = set:off reset:off clock:off tristate:off bidi:off ram:off
Logfile = dfta.log
Screen Display = off
Lockup Latch = off nolast first_clock
Latch Handling = none

Writing a Test Procedure file

Test procedure files describe the scan circuitry’s operation for the ATPG tool. They contain cycle based procedures and timing definitions that tell the DFT tools how to operate the scan structures in the design.

Before running ATPG you must be ready with a test procedure file to proceed further.

To specify a test procedure file in setup mode, use the Add Scan Groups command. The tools can also read in procedure files by using the Read Procfile command or the Save Patterns command when not in Setup mode. When you load more than one test procedure file, the tool merges the timing and procedure data.

Following are the standard test procedures: – test_setup, load_unload, shift Continue reading

Troubleshooting DRC Violations

Some rules permit user-defined handling, allowing you to specify either error, warning, note, or ignore as the handling for certain rules. (use set drc handling command)

Setting the level of Gate Data using set gate level command. The gate level can be set to design level or primitive level. When the gate level is set to design level only you will be able to correlate the reported gate to the library model available in your netlist. When the design level is set to primitive level such correlation is possible to a limited extent and the reported gate can sometimes be nowhere found in the netlist.

The set gate report command sets the type of information you want to be displayed when you report a gate. You can set that to Normal or Trace or Error_pattern or tie_value

You can use the Report Gates command to display information for selected gates, which you identify by either a gate index number or a pin pathname of a pin connected to the gate. Report Gate is a very useful command. You can list all gates of a specific type using the -type switch and a histogram of all gates by setting the type to histogram. You can report on a path between two gates. you can browse back and forth using the f and b commands respectively.

Fastscan DRC

RAM Rules: A1 to A7, A9 to A13

Clock Rules: C1 to C10 and C16

Data Rules : D1 to D11

Extra Rules: E1 to E13

General Rules: G1 to G12

Procedure Rules: P1 to P70

Trace Rules: T1 to T24

Timing Rules: W1 to W15, W17 to W18, W20 to W31

ATPG Design Rules Checking

Design rules checking generally consists of the following processes, done in the order shown:
1. General Rules Checking
2. Procedure Rules Checking
3. Bus Mutual Exclusivity Analysis
4. Scan Chain Tracing
5. Shadow Latch Identification
6. Data Rules Checking
7. Transparent Latch Identification
8. Clock Rules Checking
9. RAM Rules Checking
10. Bus Keeper Analysis
11. Extra Rules Checking
12. Scannability Rules Checking
13. Constrained/Forbidden/Block Value Calculations