What is the difference between Serail and Parallel Patterns

Parallel patterns are forced parallely (at the same instance of time) @ SI of each flop and measured @ SO. Basically these patterns are used for simulating the patterns faster. Here only two cycles are required to simulate a pattern : one to force all the flops and one for capture.
Serial patterns are the ones which are used @the tester. They are serially shifted and captured and shifted out.

Fastscan DRC

RAM Rules: A1 to A7, A9 to A13

Clock Rules: C1 to C10 and C16

Data Rules : D1 to D11

Extra Rules: E1 to E13

General Rules: G1 to G12

Procedure Rules: P1 to P70

Trace Rules: T1 to T24

Timing Rules: W1 to W15, W17 to W18, W20 to W31

Mentor Tool Concepts

A scan cell contains atleast one memory element (flip-flop or latch) that lies in the scan chain path.

Master Memory Element

The scan cell contains one and only one master memory element and one or more optional salve memory elements. The Shift Procedure in the test procedure file controls the master element.If the scan cell contains no additional independently-clocked memory elements in the scan path, this procedure also observes the master. If the scan cell contains additional memory elements, you may need to define a separate observation procedure (called master_observe) for propagating the master element’s value to the output of the scan cell.

Slave Memory Element

The slave element, an independently-clocked scan cell memory element, resides in the scan chain path. It cannot capture data directly from the previous scan cell. When used, it stores the output of the scan cell. The shift procedure both controls and observes the slave element.

Scan Chain

A scan chain is a set of serially linked scan cells

Scan Group

A scan chain group is a set of scan chains that operate in parallel and share a common test procedure file.

Scan Clocks

Scan clocks are external pins capable of capturing values into scan cell elements. Scan clocks include set and reset lines, as well as traditional clocks.

Test Procedure files

Test procedure files describe, for the ATPG tool, the scan circuitry operation within a design.

  • Define the scan circuitry for the tool.
  • Create a test procedure file to describe the scan circuitry operation. DFTAdvisor can create test procedure files for you.
  • Perform DRC process. This occurs when you exit from Setup mode.

If your design contains scan circuitry, FastScan and FlexTest require a test procedure file. You must create one before running ATPG with FastScan or FlexTest.

Model Flattening

The tools flatten the model when you initially attempt to exit the Setup mode, just prior to design rules checking. FastScan and FlexTest also provide the Flatten Model command, which allows flattening of the design model while still in Setup mode.

If a flattened model already exists when you exit the Setup mode, the tools will only reflatten the model if you have since issued commands that would affect the internal representation of the design. For example, adding or deleting primary inputs, tying signals, and changing the internal faulting strategy are changes that affect the design model. With these types of changes, the tool must re-create or re-flatten the design model. If the model is undisturbed, the tool keeps the original flattened model and does not attempt to reflatten.

By default, pins introduced by the flattening process remain unnamed and are not valid fault sites.

You should be aware that in some cases, the design flattening process can appear to introduce new gates into the design.

Learning Analysis

There are two types of learning analysis:-

Static Learning

Dynamic Learning

The ATPG tools perform static learning only once-after flattening. Because pin and ATPG constraints can change the behavior of the design, static learning does not consider these constraints. Static learning involves gate-by-gate local simulation to determine information about the design. The following subsections lists the types of analysis performed during static learning.

  • Equivalence Relationships
  • Logic Behavior
  • Implied Relationships
  • Forbidden Relationships
  • Dominance Relationships

Points to note

  • Fault modeling occurs at various level of detail. e.g. Transistor level, Gate level etc
  • FastScan does equivalence fault collapsing before going for pattern generation
  • Generally, ASIC vendors have restrictions on the number of IDDQ measurements they allow.
  • By combining IDDQ testing with traditional stuck-at fault testing, you can greatly improve the overall test coverage of your design.
  • You can turn dynamic pattern compression on with the Set Atpg Compression On command in FastScan
  • Each scan pattern is as long as the longest scan chain. So it is desirable to have balanced scan chains to the extent possible.
  • The ATE (Automatic Test Equipment) also imposes limitations on the number of allowable scan chains in a design.
  • Lock up Latches can be used in a scan chain to avoid race conditions(hold time violatoins) that occur due to clock skew
  • Always group the negedge flops and place them in the begining of the scan chain or you will have to insert a lockup latch whenever a negedge flop follows a posedge flop in a scan chain.
  • Exclude flip flops that constitute reset and clock generation circuits

What does hookup-pin mean?

Consider the scenario where you have all the test signals as shared signals except for a dedicated test_mode signal

If you define the scan enable signal as a shared signal then you must and that signal with an active high test_mode signal to produce the scan enable signal internally

Now the output of this AND gate in your design would become your scan enable hookup-pin

hookup-pin is considered by the tool as the source of scan enable and will assume that this pin is directly controllable from a primary input

Note: The term hookup-pin could be particular to Mentor tools