Points to note

  • Fault modeling occurs at various level of detail. e.g. Transistor level, Gate level etc
  • FastScan does equivalence fault collapsing before going for pattern generation
  • Generally, ASIC vendors have restrictions on the number of IDDQ measurements they allow.
  • By combining IDDQ testing with traditional stuck-at fault testing, you can greatly improve the overall test coverage of your design.
  • You can turn dynamic pattern compression on with the Set Atpg Compression On command in FastScan
  • Each scan pattern is as long as the longest scan chain. So it is desirable to have balanced scan chains to the extent possible.
  • The ATE (Automatic Test Equipment) also imposes limitations on the number of allowable scan chains in a design.
  • Lock up Latches can be used in a scan chain to avoid race conditions(hold time violatoins) that occur due to clock skew
  • Always group the negedge flops and place them in the begining of the scan chain or you will have to insert a lockup latch whenever a negedge flop follows a posedge flop in a scan chain.
  • Exclude flip flops that constitute reset and clock generation circuits

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