3 thoughts on “STA”

1. Hi Prasad,

   Clock skew is the difference in arrival time of clock at clk pins of two registerts.
   Skew is negative when data and clock are in opposite direction that means capture clock is earlier than launch clock.
   Skew is positive when data and clock are in same direction that means capture clock is later than launch clock.
   Positive skew is beneficial for Setup analysis as clock period window is increasing .
   Negative skew is beneficial for Hold analysis.

   Thanks &Regards
   Ananth

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2. Hello sir, I am student doing M.tech VLSI. My project is AMBA AHB ASIC implementation. While performing the GLS there is an error sdf unable to annotate the IO paths. Can u suggest some method to solve this problem.

   Thanks

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   • It is not possible for me to answer this question without more details.

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