Gate Level = design
Gate Report = normal
Net Resolution = wire
System Mode = setup
Tied Signal = x
Dofile Abort = on
Trace Report = off
Scan Type = mux_scan
Identification Model = clock:original disturb:on
Scan Identification = full_scan
Test_point Identification = control:0 observe:0 (scoap)
Transient Detection = on -verbose
Fault Sampling = 100.000000%
Scan-in Naming = prefix:scan_in initial:1 modifier:1 suffix:
Scan-out Naming = prefix:scan_out initial:1 modifier:1 suffix:
Test Enable Name = test_en active = high
Test Clock Name = test_clk
Scan Enable Name (Core)= scan_en active = high
Scan Enable Name (Input Partition)= scan_en_in active = high
Scan Enable Name (Output Partition)= scan_en_out active = high
Scan Clock Name = scan_clk
Scan Master Clock Name = scan_mclk
Scan Slave Clock Name = scan_sclk
Set Name = scan_set active = high muxed
Reset Name = scan_reset active = high muxed
Write Clock Name = write_clk muxed
Read Clock Name = read_clk muxed
Hold Enable Name = hold_en
Control Input Name = test_cntl
Observe Output Name = test_obs
Net Naming = net Instance Naming = uu
Test Logic = set:off reset:off clock:off tristate:off bidi:off ram:off
Logfile = dfta.log
Screen Display = off
Lockup Latch = off nolast first_clock
Latch Handling = none