After generating patterns for stuck at faults and saving the patterns into a file say pat_file
set pattern source external pat_file
set fault type iddq
add faults -all
set iddq strobe -all
select iddq patterns -max_measure 15 -threshold 10 (to select best 15 patterns that detect a min of 10 IDDQ faults each
save patterns iddq.pats
Why are stuck-at faults more efficient when applied at the circuit’s rated clock?
Timing failures can occur when a circuit operates correctly at a slow clock rate, and then fails when run at the normal system speed. In other words, when stuck-at fault tests are applied at a slower clock rate some faults which are a manifestation of timing failures could not have been detected. Such faults, if present will fail the chip ultimately. Hence At-Speed testing which is nothing but applying tests at the rated clock speed could detect such chips which are bound to fail due to timing failures.
Random Test Pattern Generation – RTPG
Deterministic Test Pattern Generation – DTPG
RTPG can never identify redundant faults while DTPG does. However, it can be useful on testable faults terminated by DTPG. Hence, as an initial step using a small number of random patterns can improve ATPG performance.
The very definition of RTPG and DTPG can prove the above statement. In DTPG, also called ATPG, there are some algorithms used to find a pattern that detects a particular fault. These ATPG algorithms have the ability to find if a fault is redundant or not. There are algorithms(called Redundancy Identification RID algorithms) which analyze the circuit without targeting any specific faults and can find many, but not all, redundant faults.
Whereas RTPG, like in Logic BIST, applies random vectors and tries to choose the best minimum possible patterns targeting a particular fault coverage. (The coverage of random patterns is observed to saturate between 60-80% of coverage)
Consider the scenario where you have all the test signals as shared signals except for a dedicated test_mode signal
If you define the scan enable signal as a shared signal then you must and that signal with an active high test_mode signal to produce the scan enable signal internally
Now the output of this AND gate in your design would become your scan enable hookup-pin
hookup-pin is considered by the tool as the source of scan enable and will assume that this pin is directly controllable from a primary input
Note: The term hookup-pin could be particular to Mentor tools