//I do not recommend the use of the below command, rather you need to specifically define all the control signals as clocks

{analyze control signals -auto_fix

or

add clocks clk

add clocks rst_n}

///////////////////////////////////////////////////////////////////////////////
// Define Scan pin naming conventions
// The scan pins will be named as chain1_scan_in, chain2_scan_in, etc and
// chain1_scan_out, chain2_scan_out eta
// Use the below command when not using the existing design pins for scan
//////////////////////////////////////////////////////////////////////////////
//setup scan pins input -prefix chain -initial 1 -modifier 1 -suffix scan_in
//setup scan pins output -prefix chain -initial 1 -modifier 1 -suffix scan_out

//Define the test mode pin
setup scan insertion -ten scan_mode
//Define the scan clock
setup scan insertion -sclk clk_120m
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//the -Isolate option can be used only for the scan enable signal of SEN type (inserted
//for regular/non-partition cells). If you specify this option, DFTAdvisor checks the global scan
//enable signal to determine if it already has fanouts. If this is true, then an AND or NOR gate is
//inserted with the second input controlled by the global test enable signal. The output of this gate
//is connected to all the new fanouts of the scan enable pin (scan enable pins of scan cells). The
//output of this gate is active for test mode and inactive for system mode. In test mode (whenever
//the global test enable pin is active), the output of this gate is identical to the scan enable signal;
//the gate acts as a buffer. Depending on the active state of the global scan enable and test enable
//////////////////////////////////////////////////////////////////////////////////////////////////////////
setup scan insertion -sen mode[0] -isolate

////////////////////////////////////////////////////////////////////////////////////////////////////
//If you specify the -Disabled option, then for gating purposes, DFTAdvisor will
//use the test enable signal to disable set and reset inputs of flip-flops, and the scan enable
//signal of SEN type to disable the write and read clocks.
////////////////////////////////////////////////////////////////////////////////////////////////////
setup scan insertion -reset rst_n -gated
setup scan insertion -set rst_n -gated
add scan pins chain1  <scan_in1>  <scan_out1>  -clock clk
add scan pins chain1  <scan_in2>  <scan_out2>  -clock clk
add scan pins chain1  <scan_in3>  <scan_out3>  -clock clk
add scan pins chain1  <scan_in4>  <scan_out4>  -clock clk
…………………………………………..

………………………………………….

set system mode dft

setup test_point identification -control 0 -observe 0 -noverbose
run
report statistics

report scan chains
report sequential instances -unidentified -nonscannable
write scan identification seq_inst_rpt -replace -identified -defined_scan
insert test logic -scan on -test_point on -ram on -number 1 -hierarchical off
write netlist -replace
write atpg setup -replace