Typical Fastscan script for ATPG pattern generation

set loggile handling <filename> -append

report version data

add scan groups grp1 <path of test procedure file>

add clocks 0 clk

add clocks 1 h_resetn

add pin constraints test_mode C1

set system mode atpg

#At this point if you encounter any drc errors, you will have to fix them before moving forward

when the above command is used the following processes occur

  1. circuit flattening
  2. learning analysis
  3. design rules checking

set fault type stuck

add faults -all

create patterns -auto

save patterns <filename> -replace -procfile -ascii -cell_placement bottom -begin 0 -all_test -mode_internal

set system mode fault

set pattern source external <pattern file path? -ascii

run

8 thoughts on “Typical Fastscan script for ATPG pattern generation

  1. “add pin constraints test_mode C1”
    When test_mode is ‘1’, you are in test mode.

    What if your scan mode enable is a bit complex logic? Consider following scenario:
    There is a circuit in which you enter scan mode if pin A rises (pos-edge) and pin {B,C,D} are {1,0,1}.

    Is it advisable to add extra gates at top level that addresses this issue OR you can do it with script too?

    Thanks,
    Avdhesh

    • You cannot specify edge sensitivity using script. You can still constrain multiple pins to put the chip into scan mode. Adding extra gates at the top level is not advisable due to various other reasons, but we can do that if necessary.
      You can still have a global test enable pin which will be anded with the BCD result to put the chip in test mode. generally you will have the BCD pins as shared pins. Keep in mind that atleast one dedicated pin is necessary for DFT.

      • sounds reasonable!

        But what if following scenario is something you want to implement:
        Test enable pin X is always low. At some point it goes high and after sometime it goes low and when it goes low, pins BCD are latched to determine which mode to go to. (e.g. 101 being scan mode, 100 being analog test mode etc etc)

        Is that possible?

  2. I guess using some kind of “user defined sequence” you can do it in tetramax (a STIL file).
    I wanted to know if fastscan can do it as well!

    • Use setup procedure in procedure file of fastscan to define your sequence. The edges are not explicitly expressed in the procedure but the clock definition implicitly expresses when tool reads your procedure file.

  3. Also,
    Do you have anything in your blog that mentions all .wgl and .vec etc files? what they do, how to interpret them and where are they used?

    • Thanks Jovin.
      So would the sequence be part of the test vector (wgl) itself (directly run on tester)?
      or would it be something that you execute first as a separate file and then execute the wgl?

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