- Untestable Faults – UT
- Unused – UU
- Tied – TI
- Blocked – BL
- Redundant – RE
- Testable Faults
- Detected – DT
- det_simulation – DS (faults detected when the tool performs fault simulation)
- det_implication – DI (faults detected when the tool performs learning analysis)
- det_robust
- det_functional
- Posdet – PD
- posdet-testable – PT (Can be detected by increasing the test generator abort limit)
- posdet-untestable – PU
- ATPG Untestable – AU (Cannot be detected by increasing the test generator abort limit)
- Undetected – UD
- Uncontrolled – UC
- Unobserved – UO
- Detected – DT
Month: September 2008
Script for generation of a selective IDDQ test set
After generating patterns for stuck at faults and saving the patterns into a file say pat_file
set pattern source external pat_file
set fault type iddq
add faults -all
set iddq strobe -all
select iddq patterns -max_measure 15 -threshold 10 (to select best 15 patterns that detect a min of 10 IDDQ faults each
save patterns iddq.pats
Points to note
- Fault modeling occurs at various level of detail. e.g. Transistor level, Gate level etc
- FastScan does equivalence fault collapsing before going for pattern generation
- Generally, ASIC vendors have restrictions on the number of IDDQ measurements they allow.
- By combining IDDQ testing with traditional stuck-at fault testing, you can greatly improve the overall test coverage of your design.
- You can turn dynamic pattern compression on with the Set Atpg Compression On command in FastScan
- Each scan pattern is as long as the longest scan chain. So it is desirable to have balanced scan chains to the extent possible.
- The ATE (Automatic Test Equipment) also imposes limitations on the number of allowable scan chains in a design.
- Lock up Latches can be used in a scan chain to avoid race conditions(hold time violatoins) that occur due to clock skew
- Always group the negedge flops and place them in the begining of the scan chain or you will have to insert a lockup latch whenever a negedge flop follows a posedge flop in a scan chain.
- Exclude flip flops that constitute reset and clock generation circuits
Points to Probe
- what is a psuedo stuck at fault model?
- Add Pin Constraint command in FastScan
- Update Implication Detections command in FastScan
Why At-speed testing?
Why are stuck-at faults more efficient when applied at the circuit’s rated clock?
Timing failures can occur when a circuit operates correctly at a slow clock rate, and then fails when run at the normal system speed. In other words, when stuck-at fault tests are applied at a slower clock rate some faults which are a manifestation of timing failures could not have been detected. Such faults, if present will fail the chip ultimately. Hence At-Speed testing which is nothing but applying tests at the rated clock speed could detect such chips which are bound to fail due to timing failures.
Random Vs Deterministic Test Pattern Generation
Random Test Pattern Generation – RTPG
Deterministic Test Pattern Generation – DTPG
RTPG can never identify redundant faults while DTPG does. However, it can be useful on testable faults terminated by DTPG. Hence, as an initial step using a small number of random patterns can improve ATPG performance.
The very definition of RTPG and DTPG can prove the above statement. In DTPG, also called ATPG, there are some algorithms used to find a pattern that detects a particular fault. These ATPG algorithms have the ability to find if a fault is redundant or not. There are algorithms(called Redundancy Identification RID algorithms) which analyze the circuit without targeting any specific faults and can find many, but not all, redundant faults.
Whereas RTPG, like in Logic BIST, applies random vectors and tries to choose the best minimum possible patterns targeting a particular fault coverage. (The coverage of random patterns is observed to saturate between 60-80% of coverage)
What does hookup-pin mean?
Consider the scenario where you have all the test signals as shared signals except for a dedicated test_mode signal
If you define the scan enable signal as a shared signal then you must and that signal with an active high test_mode signal to produce the scan enable signal internally
Now the output of this AND gate in your design would become your scan enable hookup-pin
hookup-pin is considered by the tool as the source of scan enable and will assume that this pin is directly controllable from a primary input
Note: The term hookup-pin could be particular to Mentor tools
Common sources of Xs in a design
- Unconnected Pins
- Uncontrolled Primary Inputs
- Analog modules
- Undefined or Uninitialized logic
- Bus Contention
What is deterministic ATPG? What is its counterpart?
ATPG is by definition deterministic. Deterministic ATPG would amount to using redundant terms. The only non-deterministic counterpart is pseudo-random pattern testing (Logic BIST).
-Courtesy http://www.dftforum.com
-By Steve Pateras
Scan Process
The operating procedure of the scan circuitry is as follows:
1. Enable the scan operation to allow shifting (to initialize scan cells).
2. After loading the scan cells, hold the scan clocks off and then apply stimulus to the primary inputs.
3. Measure the outputs.
4. Pulse the clock to capture new values into scan cells.
5. Enable the scan operation to unload and measure the captured values while simultaneously loading in new values via the shifting procedure (as in step 1).
Prasad Addagarla 